Description
Astera Labs is hiring an onsite Tech Lead PCB Layout Engineer to design complex PCBs for AI and machine-learning connectivity products. The role covers high-speed interfaces, power, high-density interconnect, signal integrity, power integrity, DFT, and DFM, and requires a bachelor’s degree in electrical engineering or a similar field, at least 10 years of experience with complex PCBs, proficiency with PCIe, Ethernet, DDR, advanced HDI technologies, and EDA tools such as Cadence Allegro, Polar SI9000, CAM350, and AutoCAD.
