Description
Astera Labs is hiring a Tech Lead Physical Design engineer in Bengaluru, India to own end-to-end physical design implementation for complex, high-performance ASIC/SoC designs. The role covers floorplanning, placement, CTS, routing, timing closure, physical verification, ECO, STA, congestion and signal-integrity analysis, PPA optimization, design signoff, and automation. Candidates need a bachelor's or master's degree in a relevant engineering field, strong ASIC physical design experience, EDA-tool expertise, and scripting skills; advanced-node, full-chip, multi-voltage, and tapeout experience are preferred.
