Description
Astera Labs is hiring a Principal Engineer, Static Timing Analysis in Hyderabad to own full-chip STA signoff and timing closure for complex AI connectivity SoCs. The role drives timing convergence across advanced process nodes, resolves setup, hold, CDC, crosstalk, noise, and IR-aware timing violations, develops STA methodology and automation flows, partners with physical design, RTL, DFT, CAD, and package teams, and mentors STA engineers. Candidates need a bachelor's degree in electrical or electronics engineering, at least six years of STA experience on complex ASIC/SoC designs, full-chip signoff on at least one tapeout at 7nm or below, expertise with PrimeTime and SDC, and scripting proficiency.
