Description
Astera Labs is hiring a Tech Lead – Verification Methodology / CAD / Automation Engineer to lead verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams. The role owns scalable simulation, regression, coverage, debug, and signoff frameworks; develops Python, Tcl, Perl, Shell, and C++ automation; builds UVM/SystemVerilog environments; integrates EDA tools; improves regression performance; and mentors verification engineers. The position requires 6–12 years of relevant experience, strong verification and automation skills, and a degree in electronics, electrical engineering, computer science, computer engineering, VLSI, or a related discipline.
