Description
The role involves physical design of blocks for TPU chips, contributing to subchip and individual-block design from RTL to GDS, collaborating with RTL and physical-design teams to optimize power, performance, and area, and conducting feasibility studies and optimization runs for new microarchitectures. It requires a bachelor's degree in a relevant engineering or computer science field or equivalent practical experience, plus at least six years of physical-design experience; a master's or PhD, scripting-language experience, constraints and synthesis experience, and SoC or ASIC design experience are preferred.
