Description
Astera Labs is hiring a Technical Lead Physical Design Engineer to lead timing closure and sign-off for complex connectivity ASICs used in cloud service providers, server and network OEMs. The role owns STA across RTL through sign-off, manages I/O timing budgets, applies advanced TSMC 7nm and below sign-off methodologies, and collaborates with RTL, physical design, and verification teams to achieve full-chip timing convergence. The position is fully on-site and in-person, with a base salary of CAD 140,000–180,000.
