Description
As a Technical Lead Physical Design Engineer - Power Integrity at Astera Labs, you will be responsible for owning IR drop and electromigration (IR/EMIR) analysis and closure across the company's connectivity ASIC portfolio. You will drive power integrity from early floorplan through tapeout, ensuring stable power delivery, meeting foundry sign-off criteria, and preventing long-term reliability issues in production silicon. This role involves close collaboration with various engineering teams to achieve successful design convergence.
