Description
The ASIC STA Engineer will own timing-related activities across SoC design, including timing sign-off, STA and sign-off flow development, IP and block-level timing constraints, and timing closure from synthesis through physical design. The role collaborates with RTL designers, CAD engineers, and physical design teams, develops timing constraints and flows, and addresses pessimism and timing analysis issues. A bachelor's degree in Electrical Engineering is required, while ASIC timing closure methodology, STA tools, timing corners, process variations, signal integrity, SDC constraint management, and Tcl or Perl scripting are preferred qualifications.
