Physical Design Engineer - Full Chip Implementation at Etched

Etched is hiring a top-level Physical Design Engineer to own full-chip implementation from synthesis through GDSII completion. The role leads clocking, MMMC timing closure, timing constraints and ECO closure, physical verification, and tapeout signoffs, while collaborating with RTL designers and using tools such as Cadence Innovus, Genus, Synopsys PrimeTime, Tempus, Pegasus, and Calibre. The position is fully in-person in San Jose and offers medical, dental, and vision coverage, a medical-benefit waiver credit, housing subsidy, relocation support, wellness benefits, daily meals, and an unlimited compute budget.