TPU ASIC Design Engineer at Google

Seniority in posting: Mid

Compensation

$138,000 – $197,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: mid
Posted: Aug 21, 2026

Description

Google is hiring a TPU ASIC Design Engineer to develop and verify custom silicon for AI/ML hardware acceleration. The role involves improving chip-level design, designing and documenting ASIC blocks with functionality and timing, and collaborating with software teams on interfaces and documentation. Candidates need a bachelor's degree in a relevant engineering or computer science field, four years of custom silicon design experience, and RTL design experience with Verilog or SystemVerilog. The position offers a US salary of $138,000–$197,000 plus a 15% bonus target, equity, and benefits.

Required Skills

Custom silicon design
RTL design
Verilog
SystemVerilog
Computer architecture
Python

Additional Information

Minimum Education: Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience
Required Previous Experiences: 4 years of custom silicon design experience
RTL design experience with Verilog or SystemVerilog
Preferred Qualifications: Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture
Experience interacting with software, architecture, and other cross-functional teams
Experience with a scripting language such as Python or Perl
Experience applying engineering best practices, including code review, testing, and refactoring
Knowledge of processor design, accelerators, memory hierarchies, and machine learning algorithms
Knowledge of high-performance and low-power design techniques