TPU ASIC Hardware Engineer at Google

Google is hiring a TPU ASIC Hardware Engineer to create and own microarchitecture for compute accelerator intellectual property, develop and maintain design blocks, implement SystemVerilog RTL, and support verification, physical design, and timing closure. The role requires a bachelor's degree in a relevant engineering or computer science field and eight years of digital design experience using SystemVerilog RTL, along with experience in power, performance, and area optimization. Compensation is $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits.