Transistor-Level Analog Design Engineer, SerDes Clocking Subsystem at d-Matrix

Department: Hardware Engineering

Compensation

$155,000 – $250,000/yr

Setup: Hybrid
Location: California
Level: senior
Posted: Aug 19, 2026

Description

d-Matrix is seeking a transistor-level analog design engineer to own the clocking subsystem of its high-speed SerDes IO chiplet, including PLL, DLL, phase interpolator, clock distribution, and CDR loop design. The role covers specification-to-silicon characterization, process-node porting, jitter and phase-noise budgeting, verification, layout, and bench characterization, with close collaboration across datapath, DSP, digital, and firmware teams. Candidates need an electrical engineering degree, at least five years of analog and mixed-signal design experience, and demonstrated ownership of low-jitter clocking blocks through silicon.

Required Skills

Analog design
PLL architecture
Phase interpolation
CDR dynamics
Jitter budgeting
Cadence Virtuoso
Spectre
Verilog-A
Deep-submicron layout

Additional Information

Minimum Education: Bachelor's, master's, or PhD in Electrical Engineering
Required Previous Experiences: At least 5 years of hands-on analog and mixed-signal circuit design experience
Ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link
Circuit design experience in advanced FinFET or GAA process nodes
Silicon bring-up and bench debug experience with phase noise analyzers, high-speed scopes, and BERTs
Preferred Qualifications: Die-to-die interconnect experience with UCIe, BoW, or a proprietary D2D PHY
Forwarded-clock and matched-source-synchronous architectures with embedded-clock CDR
Digital and hybrid PLL/CDR implementations with digital calibration
Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, and PCIe Gen6/Gen7 specifications
Experience porting a clocking block across process nodes
Participation in or contribution to standards bodies