Description
The Formal Verification CAD Engineer will develop, maintain, and enhance formal verification tooling and flows supporting Jasper reset analysis, sequential equivalence checking, formal proofing, low-power, connectivity, and coverage applications. The role also involves debugging vendor tools, profiling and tuning applications, developing continuous integration and deployment pipelines, managing large-scale compute clusters, and collaborating with CAD and functional front-end teams. Candidates need scripting experience in Python, Perl, Kotlin, or TCL; software development with test-in-mind; Verilog and System Verilog knowledge; a bachelor's degree; and at least three years of relevant industry experience.
