Validation / Verification Eng, Manager - 18378 at Synopsys

Language

Location: Oeiras
Type: Full-time
Level: lead/mgmt
Posted: Aug 13, 2026

Description

Synopsys is hiring a Silicon Validation Manager to lead silicon validation operations for high-speed analog IP at its Lisbon site. The role manages lab resources, test execution, SerDes characterization, silicon debugging, validation reporting, custom test hardware, and the development of a validation engineering team. Candidates need at least five years of analog or mixed-signal silicon validation experience, team-management experience, a relevant engineering degree, strong analog and SerDes knowledge, and proficiency with test automation tools such as MATLAB or Python.

Required Skills

Silicon validation
SerDes validation
Signal integrity
Test automation
MATLAB
Python
FPGA testing
Verilog
VHDL

Additional Information

Minimum Education: Degree in Electronic Engineering, Electrical Engineering, or a related technical discipline
Required Previous Experiences: 5+ years of silicon validation, test, or characterization experience for analog or mixed-signal integrated circuits
Experience managing technical teams, including project planning, resource allocation, performance evaluation, and engineer development
Experience building team capability and delivering results while maintaining technical quality
Experience managing validation projects from test plan development through final reporting
Preferred Qualifications: Experience with FPGA-based test systems
Familiarity with Verilog or VHDL for custom test logic