Description
Synopsys is hiring a VC Formal Application Engineer to lead technical deployments of VC Formal at customer sites, assess semiconductor verification environments, recommend formal methodologies, diagnose tool-performance and proof-convergence issues, optimize testbench modeling, deliver formal-verification training, and communicate customer priorities to R&D. The role requires 4 to 8 years of hands-on formal-verification experience in semiconductor design or verification, including expertise in property checking, sequential equivalence, formal coverage, connectivity checking, and testbench optimization.
