Description
Synopsys is hiring a Verification Applications Engineer in Hyderabad to support customers using VCS and Verdi, diagnose simulation failures, analyze SystemVerilog and UVM testbenches, resolve coverage and low-power verification issues, automate workflows with Tcl, Python, or Perl, and guide customers through tape-out cycles. The role collaborates with Synopsys R&D teams, works across timezones, and occasionally requires travel to customer sites. Candidates need a bachelor's degree in electronics engineering or a related field with at least two years of verification or digital design experience, or a master's degree in electronics, along with digital design, simulation, scripting, and communication skills.
