Description
AMD is seeking a highly motivated individual to join their System Management Unit (SMU) IP team. The successful candidate will develop comprehensive block-level verification testplans, create testbenches and test cases using SystemVerilog/UVM methodology, and produce reusable verification IP. They will also support subsystem and SOC-level verification. The ideal candidate will possess excellent knowledge of design verification methodologies like OVM/UVM/System Verilog, solid experience with simulation model creation and testbench building, and strong communication skills.
