Verification Engineer at Oriole Networks

Setup: Hybrid
Location: London, England
Type: Full-time
Level: senior
Posted: Jun 4, 2026

Description

Oriole Networks is hiring an experienced Verification Engineer to develop high-speed network interfaces between xPUs and a proprietary network. The role involves architecting verification infrastructure, planning and executing verification strategies, building module- and system-level testbenches, driving functional coverage closure, and supporting hardware validation and debugging. The position requires extensive FPGA or ASIC verification experience, strong SystemVerilog and scripting skills, familiarity with Questa and VCS, and knowledge of networking and hardware interfaces.

Required Skills

FPGA/ASIC verification
SystemVerilog
TCL/Python scripting
Questa/VCS
Functional coverage
Constrained random
Formal verification
100Gbps networking

Additional Information

Minimum Education: Bachelor's or Master's degree in electronics engineering, physics, or a relevant field, or equivalent industry experience
Required Previous Experiences: Extensive industry experience in FPGA or ASIC verification, ideally for GPU/CPU interfacing and networking at 100Gbps or above
Experience verifying at unit and system level, particularly for FPGA solutions and production-quality IP
Experience architecting verification environments and infrastructure
Experience using Questa and VCS
Experience with formal verification tools such as Questa Formal and JasperGold
Preferred Qualifications: GPU/CPU interfacing and networking experience at 100Gbps or above
Production-quality IP experience
Experience with UALink, NVLink, PCIe, RDMA, or CXL
Translation Company Name: Oriole Networks