Description
Quantum Machines is hiring a Verification Engineer to own and execute hardware/software verification for quantum-computing control-system products. The role includes building verification environments and infrastructure from scratch, integrating verification IP for DDR, PCIe, and AXI, defining constrained verification sequences and test plans, integrating reference models, and collaborating with hardware engineers, software engineers, and quantum physicists. The position requires 3–5 years of experience with UVM and SystemVerilog; knowledge of hardware/software interaction and C, C++, Python, or SystemC is advantageous.
