Description
Synopsys is seeking a highly experienced Verification Engineer to design, develop, and maintain Verification IP using SystemVerilog and UVM. The role involves creating comprehensive verification plans, coding sequences and checkers for coverage-based verification, debugging complex simulation failures, and supporting customers during deployment. This engineer will collaborate with Design IP teams and R&D engineers to ensure VIP capabilities align with product roadmaps and customer needs, ultimately contributing to global semiconductor development workflows.
