Description
Apple is seeking an engineer to bridge next-generation platform technology with design verification methodology and tooling. The role focuses on improving simulation throughput for DV workflows through testbench design, RTL modifications, EDA-tool integration, infrastructure improvements, and platform R&D. Responsibilities include evaluating and maintaining high-performance RTL simulation tooling, diagnosing issues with EDA tools, and collaborating with silicon engineering and design verification teams. The position requires a bachelor’s degree in a relevant engineering field, experience with SystemVerilog and EDA tooling, and software development and scripting experience.
