Description
Lyte is hiring an experienced Wafer-Level Test (WLT) Engineer/Lead based in Taiwan, with Hsinchu preferred. The role owns CP and wafer-sort test for custom mixed-signal CMOS silicon, develops and maintains ATE test programs on Advantest or Teradyne platforms, brings up and debugs silicon, supports production transfers to OSAT partners, analyzes yield data, and coordinates with chip design and partner teams. The position requires a bachelor's degree, at least five years of ATE test-program development experience, programming skills, strong data-analysis and documentation practices, and regular travel within Taiwan and occasionally across Asia.
