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Wafer/Package level testing engineer at STMicroelectronics

Department: Techno Rel. & Failure Analysis

Compensation

€38,000 – €45,000/yr

Setup
On-site
Level
mid
Posted

Description

The role plans, executes, monitors, analyzes, and reports electrical wafer-sorting and final-test data for reliability, supporting prototypes of discrete power technologies such as SiC, IGBT, and GaN. It also involves bench characterization of power devices, early evaluation of MOSFET device physics, and technology qualification of electrical static performance. The position requires a master's degree in physics, material science, or electrical/physical engineering, two years of experience, knowledge of reliability and semiconductor physics, English proficiency, and problem-solving and teamwork skills. The expected gross annual salary is €38,000–€45,000 RAL plus variable pay.

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