Description
Microsoft is hiring a Design Verification Engineer for its Compute Silicon & Manufacturing Engineering organization to verify components used in Fabric Interconnect. The role involves defining verification strategies and test plans, developing UVM-based or formal verification environments, running and debugging simulations, applying random-stimulus and coverage-based techniques, improving verification efficiency, applying generative AI to verification work, and mentoring others. Candidates need a relevant master's degree with at least one year of technical engineering experience, or a relevant bachelor's degree with at least two years of experience, or equivalent experience. The typical U.S. base pay range is USD 102,100–202,200 per year, with higher ranges for the San Francisco Bay area and New York City metropolitan area.
