Description
Microsoft is hiring a Design Verification Engineer for its Silicon, Cloud Hardware, and Infrastructure Engineering organization to verify components used in Fabric Interconnect. The role involves defining verification strategies and test plans, developing UVM-based or formal verification environments, running and debugging simulations, applying random-stimulus and coverage-based techniques, improving verification efficiency, and applying generative AI to verification work. Candidates need a relevant master's degree plus at least one year of technical engineering experience, or a relevant bachelor's degree plus at least two years of experience, or equivalent experience. The typical U.S. base pay range is USD 102,100–202,200 per year, with higher ranges for the San Francisco Bay area and New York City metropolitan area.
