Senior Engineer, Digital Design Engineering at Analog Devices, Inc.

Compensation

$112,020 – $166,668/yr

Setup: Hybrid
Location: Colorado Springs, Colorado
Type: Full-time
Level: Senior

Description

Analog Devices, Inc. is seeking a Senior Engineer, Digital Design Engineering to develop cutting-edge solutions for various industries like healthcare, communications, aerospace, and defense. The role involves designing and verifying integrated circuits, collaborating with cross-functional teams throughout the product development lifecycle, and ensuring designs meet performance standards. Responsibilities include writing user guides, testing designs, and contributing to documentation.

Required Skills

digital design methodologies
RTL design
Lint
CDC
simulations
synthesis
Cadence or Synopsis tools
verification tools and techniques
Verilog
System Verilog
coverage analysis
transaction level modelling
pseudo and constrained random techniques
assertion based and formal verification techniques
System Verilog
digital design development and tapeout activities
debugging
gate level simulations
evaluation

Additional Information

Required Previous Experiences: 24 months of experience as a Digital Design Engineer or related occupation performing digital or mixed signal design and verification.
Preferred Qualifications: Demonstrated expertise (DE) applying digital design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products.
DE running simulations, synthesis, and CDC using Cadence or Synopsis tools.
DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow.
DE working with verification plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
DE participating in all phases of digital design development and tapeout activities (architecture, debug, gate level simulations, and evaluation).